Computer systems use memory devices, such as dynamic random access memory (“DRAM”) devices, to store data that are accessed by a processor. These DRAM devices are normally used as system memory in a computer system. In a typical computer system, the processor communicates with the system memory through a processor bus and a memory controller. The system memory is typically arranged in memory modules each having multiple memory devices, and the memory modules are coupled through a memory bus to the memory controller. The processor issues a memory request, which includes a memory command, such as a read command, and an address designating the location from which data or instructions are to be read or to which data or instructions are to be written. The memory controller uses the command and address to generate appropriate command signals as well as row and column addresses, which are applied to the system memory through the memory bus. In response to the commands and addresses, data are transferred between the system memory and the processor. The memory controller is often part of a system controller, which also includes bus bridge circuitry for coupling the processor bus to an expansion bus, such as a PCI bus.
A high data bandwidth is a desirable capability of memory systems. Generally, bandwidth limitations are not related to the memory controllers since the memory controllers sequence data to and from the system memory as fast as the memory devices allow. One approach to increasing bandwidth is to increase the speed of the memory data bus coupling the memory controller to the memory devices. However, memory devices have not been able to keep up with increases in the data bandwidth of memory controllers and memory data buses. In particular, the memory controller must schedule all memory commands to the memory devices in a manner that allows the memory devices to respond to the commands. Although these hardware limitations can be reduced to some degree through the design of the memory device, a compromise must be made because reducing the hardware limitations typically adds cost, power, and/or size to the memory devices, all of which are undesirable alternatives. While memory devices can rapidly handle “well-behaved” accesses at ever increasing rates, for example, sequel traffic to the same page of a memory device, it is much more difficult for the memory devices to resolve “badly-behaved traffic,” such as accesses to different pages of the memory device. As a result, the increase in memory data bus bandwidth does not result in a corresponding increase in the bandwidth of the memory system.
One approach to increasing the bandwidth of memory systems has been to use bank interleaving. In bank interleaving, two or more memory banks are accessed alternately so that preparations can be made to access data in one memory bank while data are being written to or read from another bank. The bandwidth of the memory system can be increased using this approach because it is not necessary to wait for memory access preparations like precharging to be completed before data can be coupled to or from the memory device. However, the memory bandwidth improvements that can be obtained with bank interleaving are limited by the inability to write to or read from multiple banks of memory at the same time. While preparations can be made to read from or write to a bank while data are being read from or written to another bank, it is not possible to actually couple the read data from or the write data to the bank until the access to the other bank has been completed.
An approach to increasing memory bandwidth that has some similarities to bank interleaving is memory device interleaving. In memory device interleaving, different memory devices are alternately accessed. As a result, preparations can be made to access one memory device while data is being read from or written to the other memory device. While memory device interleaving increases the memory bandwidth in a manner similar to the manner in which bank interleaving increases memory bandwidth, it suffers essentially the same limitations. In particular, it is not possible to actually couple the read data from or the write data to the memory device until the transfer of data to or from the other memory device has been completed.
In addition to the limited bandwidth of memory devices, the performance of computer systems is also limited by latency problems that increase the time required to read data from memory devices. More specifically, when a memory device read command is coupled to a system memory device, such as a synchronous DRAM (“SDRAM”) device, the read data cannot be output from the SDRAM device until a delay of several clock periods has occurred. Although SDRAM devices can synchronously output burst data at a high data rate, the delay in initially providing the data can significantly slow the operating speed of a computer system using such SDRAM devices. These latency issues generally cannot by alleviated to any significant extent by simply increasing the memory data bus bandwidth.
The memory latency problem is greatly exacerbated by read accesses alternating with write accesses, a situation known as “read/write turnarounds.” When a memory controller issues a read command to a memory device, the memory device must couple read data from a memory array to external data bus terminals of the memory device. The read data must then be coupled through a data bus portion of the memory bus from the memory device to the memory controller. It is only then that the memory controller can couple write data to the memory device through the data bus to initiate a write memory access.
Opening the page requires the coupling of memory command and a row address and a column address from the memory controller to the memory device. In response to the read address, the memory device must equilibrate the corresponding row, turn on access transistors for that row, and allow a sense amplifier for each column to sense the voltage that a respective memory cell couples to the sense amplifier. All of this can take a considerable period of time. For this reason, a read operations from a closed page and read/write turnarounds can prevent memory devices from even coming close to achieving the data bandwidths that are possible with high speed memory controllers and memory buses.
There is therefore a need for a memory device and memory system that allows a higher data bandwidth to be achieved.